Prediction Tree of Verilog

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Prediction Tree of Verilog

Text based Description

[1] root
  | [2] video_processing in N: N (n = 192290, err = 0.0%)
  | [3] video_processing in Y
  | | [4] Flash in N
  | | | [5] Tcl in N: N (n = 50, err = 2.0%)
  | | | [6] Tcl in Y: Y (n = 7, err = 14.3%)
  | | [7] Flash in Y: Y (n = 10, err = 10.0%)
 
  Number of inner nodes: 3
  Number of terminal nodes: 4

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Created by Mr. Cyrus Wong, Data Scientist.
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